JPH0553310B2 - - Google Patents
Info
- Publication number
- JPH0553310B2 JPH0553310B2 JP1234152A JP23415289A JPH0553310B2 JP H0553310 B2 JPH0553310 B2 JP H0553310B2 JP 1234152 A JP1234152 A JP 1234152A JP 23415289 A JP23415289 A JP 23415289A JP H0553310 B2 JPH0553310 B2 JP H0553310B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- plating film
- plating
- lead frame
- noble metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Led Device Packages (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1234152A JPH02110982A (ja) | 1989-09-08 | 1989-09-08 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1234152A JPH02110982A (ja) | 1989-09-08 | 1989-09-08 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02110982A JPH02110982A (ja) | 1990-04-24 |
JPH0553310B2 true JPH0553310B2 (en]) | 1993-08-09 |
Family
ID=16966465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1234152A Granted JPH02110982A (ja) | 1989-09-08 | 1989-09-08 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02110982A (en]) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07104183B2 (ja) * | 1990-11-30 | 1995-11-13 | 日本電装株式会社 | 自発光指針 |
JP4316019B2 (ja) * | 1996-10-01 | 2009-08-19 | 株式会社東芝 | 半導体装置及び半導体装置製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5571045A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Lead frame |
JPS574183A (en) * | 1980-06-10 | 1982-01-09 | Toshiba Corp | Metallic thin strip for installing semiconductor light-emitting element |
-
1989
- 1989-09-08 JP JP1234152A patent/JPH02110982A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH02110982A (ja) | 1990-04-24 |
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